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Paged
CMOS
E
Internal Control Timer
1 to 64-Byte Page Write Operation
200
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel's advanced nonvolatile CMOS technology, the device offers access
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,
the CMOS standby current is less than 200
17 are DON'T CONNECT.
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writ-
ing of up to 64-bytes simultaneously. During a write cycle,
the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inad-
vertent writes. The device also includes an extra 64-bytes
of E
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
with Respect to Ground .............-0.6V to V
with Respect to Ground ................... -0.6V to +13.5V
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
allows 1 to 64-bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 63 addi-
tional bytes. Each successive byte must be written within
150
mence the internal programming operation. All bytes dur-
ing a page write operation must reside on the same page
as defined by the state of the A6 - A14 inputs. For each
WE high to low transition during the page write operation,
A6 - A14 must be the same.
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
against inadvertent writes to the AT28C256 in the follow-
ing ways: (a) V
holding any one of OE low, CE high or WE high inhibits
write cycles; (d) noise filter - pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
data protection feature has been implemented on the
AT28C256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C256 is
shipped from Atmel with SDP disabled.
three write commands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
sequence and after t
noted, that once protected the host may still perform a
byte or page write to the AT28C256. This is done by pre-
ceding the data to be written by the same 3-byte command
sequence used to enable SDP.
mand sequence is issued. Power transitions do not dis-
able SDP and SDP will protect the AT28C256 during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifica-
tions. The data in the enable and disable command se-
quences is not written to the device and the memory ad-
dresses used in the sequence may be written with data in
either a byte or page write operation.
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
Temperature (Case)
E
be written to or read from in the same manner as the regu-
lar memory array.
be erased using a 6-byte software code. Please see Soft-
ware Chip Erase application note for details.
Address, whichever
occurred first
Measurement Level
