The Turbo IC 25C128/25C256 is a serial 128K/256K
EEPROM fabricated with Turbo's proprietary, high reliabil-
ity, high performance CMOS technology. It's 128K/256K of
memory is organized as 16384/32768 x 8 bits. This device
offers a flexible byte write and a faster 64-byte page write. It
also offers significant advantages in low power and low VCC
pin PDIP or 8-pin SOIC package. Pin #1 is the Chip Select
(CS). Pin #2 is the Serial Output (SO). Pin #3 is Write Pro-
tect (WP). Pin #4 is the ground (Vss). Pin #5 is the Serial
Input (SI). Pin #6 is the serial clock (SCK). Pin #7 is the
Hold Input (HOLD)., and Pin #8 is the power supply (Vcc)
Interface (SPI), allowing operation on a three-wire bus. The
Turbo IC 25C128/25C256 has separate data input (SI) and
data output (SO) pins. The serial clock (SCK) pin controls
the data transfer. Access to the device is controlled through
the chip select (CS) input.
hibit feature where the user has the option of inhibiting writes
to 3 different sizes of the memory array. A write protect
(WP) pin is provided to prevent inadvertent writes to the
status register. The Turbo 25C128/25C256 can also be put
on hold during any serial communication by asserting the
hold (HOLD) pin.
ˇ Extended Power Supply Voltage
(Vcc = 2.7V to 3.6 V) (Vcc = 4.5V to 5.5V)
ˇ SPI (Serial Peripheral Interface) Bus
ˇ Support Byte Write and Page Write (64 Bytes)
ˇ Automatic 64 Byte Page write Operation (max. 10 ms)
Internal Data Latches for 64 Bytes
ˇ High Reliability CMOS Technology with EEPROM Cell
Data Retention : 100 Y
ˇ 2.1 Mhz clock rate
ˇ 8 pin JDEC 300 mil wide PDIP and 8 pin 150 mil wide
The SCK input pin controls the serial bus timing
of the data transfer that occurs on the serial in-
put pin and the serial output pin.
The HOLD input pin pauses the data transfer,
allowing the host to service higher-priority inter-
rupts. Once the device is selected and serial
communication between the controller and the
device is under way, a high to low transition on
HOLD while SCK is low freezes the serial com-
munication. Transitions on the SI and SCK pins
are ignored, and the SO pin is at high imped-
ance. To resume the serial communication,
HOLD is set high while SCK is low. The serial
sequence restarts from where it had stopped with
no loss of continuity. HOLD should always be
high during normal operation.
The WP input pin controls the status register write
protect feature. For normal read and write op-
erations, the WP pin is held high. When the WP
pin is low and the WPEN bit in the status register
is "1", all write operations to the status register
are inhibited. The WP pin function is blocked
when the WPEN bit is "0". This feature allows a
user to install the Turbo IC 25C128/25C256 into
a system with the WP pin tied to ground and still
be able to program the status register. The WP
pin function will then be enabled when the WPEN
bit is set to "1".
The SI input pin accepts all opcodes, addresses,
and write data to be input into the Turbo IC
25C128/25C256. The data is latched on the ris-
ing edge of the serial clock.
The CS input pin selects the Turbo IC 25C128/
25C256. A high to low transition on CS selects
the Turbo IC 25C128/25C256, and keeping CS
low keeps the device activated. When CS is
brought high, the Turbo IC 25C128/25C256 is de-
selected and the serial output pin (SO) is at high
The serial output pin is a push-pull serial data
output. During read, the data is shifted out onto
SO on the falling edge of the serial clock.
8-bit status register. The instruction register stores one of the
operation codes defined in Table 1.
and initiates the data transfer. The Turbo IC 25C128/25C256 are
the slave devices in all applications. The master selects the
Turbo IC 25C128/25C256 by pulling CS of the device low. Once
the device is active, the master sends the operation code into
the instruction register.
end of the write cycle of a write instruction. Therefore, the
WREN instruction precedes all write instructions because the
write enable latch must be set before a write can be executed.
The WRDI instruction is used to clear the write enable latch
Turbo IC 25C128/25C256. The contents of the status register is
given in Table 2.
Table 2 Status Register Contents
Bit 7 Bit 6
WPEN X X X
WPEN to a "1" enables the hardware write protect, and a "0"
disables the hardware write protect. This bit is non-volatile
and is programmed by the WRSR instruction. This bit works
in conjunction with the the Write Protect (WP) pin to control
the hardware write protect feature. Hardware write protection
is enabled when the WP pin is low and the WPEN bit is "1".
Hardware write protection is disabled when either the WP pin
is high or the WPEN bit is "0". When the hardware write
protection is on, only the writes to the the non-volatile bits
(WPEN, BP1, BP0) are disabled. It is noted that the write
enable latch must also be set before the non-volatile bits
can be programmed.
These bits are read-only. BP[1:0] are the block write protect bits.
These bits specifies which blocks in the memory array are
write protected, as indicated in Table 3. These bits are non-
volatile and are programmed by the WRSR instruction.
means that the write enable latch is set. A "0" means that
the write enable latch is cleared. This bit is read-only.
memory array. A "1" means that the write cycle is in progress.
A "0" means the write cycle has finished and the device is
ready for the next instruction. This bit is read-only.
Status Register Fraction of Array Write Protected Memory Blocks
BP1 BP0 Write Protected
instruction. The write protect enable bit, the block write
protect bit, the write enable status, and the busy status of
the Turbo IC 25C128/25C256 can be found through RDSR. Three bits
of the status register can be altered by the WRSR instruction. The
write protect enable bit can be set to enable the hardware write
protect, and the block write protect bits can be set to control
the number of blocks to be write protected, according to Table 3.
When the status register is being programmed, the RDSR instruction
can be used to check the status of the BSY bit. All the other bits
will read back ones during an internal write cycle.
The data in the memory array of the Turbo IC 25C128/25C256
can be read as follows: The master pulls the CS pin of the
Turbo IC 25C128/25C256 low, and issues a READ instruction
to the SI pin, which is loaded into the instruction register.
The two address bytes of the memory location to be read are
sent next, which are loaded into the address counter. The two
most significant bits of the address are don't cares for 25C128
while the first MSB of the address is don't care for the 25C256. The
data byte in the memory is shifted out onto the SO pin on the
falling edge of SCK. After the data byte is shifted out, the address
counter is incremented by one. The next data byte is shifted
out. The sequential read continues for as long as the master
provides the clock and keeps CS low. When the address
counter reaches the highest address, it rolls over to the zero
address (0). The read is terminated by bringing CS high.
selected Turbo IC 25C128/25C256 as follows: The master pulls the
CS pin of the selected Turbo IC 25C128/25C256 low, and issues a
WREN instruction to the SI pin, which is loaded into the instruction
register. Then the master brings CS high to set the WREN latch. The
master pulls the CS pin low, and issues the WRITE instruction to the SI
pin, which is loaded into the instruction register. The two address bytes
of the memory location to be written are sent next, which are loaded
into the address counter. The first most significant bit of the address
is a don't care for the 25C256 and the first two MSBs are don't cares
for the 25C128. The data byte to be written is sent next. The data byte
is stored in a data byte latch. The address counter is incremented by
one after the data byte is shifted in. Up to 64 data bytes can be sent
before a write cycle is necessary. To start the internal write cycle, the
CS must be brought high after the least significant bit (D0) of the last
data byte has been loaded. If CS is brought high at any other time, the
write cycle will not start.
master pulls CS low, and issues the RDSR instruction. The contents
of the status register is shifted out onto the SO pin. The BSY
bit can be checked. If BSY is "1", the write programming is still
in progress. If BSY is "0", the write programming has finished.
At the end of the write cycle, the WREN latch is automatically
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