and erasable read only memory (PEROM) fabricated with
Turbo IC's proprietary, high reliability, high performance
CMOS technology. Its 1024K bits of memory are organized
as 128K by 8 bits. The device offers access time of 120 ns
with power dissipation below 330 mW.
abling the entire memory to be programmed typically in less
than 10 seconds. During a program operation, the address
and a complete sector (128 bytes) of data are internally
latched, freeing the address and data bus for other micro-
processor operations. The programming process is auto-
matically controlled by the device using an internal control
timer. Data polling on I/O7 or a Toggle bit can be used to
detect the end of a programming cycle. In addition, the
29C010 includes an user-optional software data write mode
offering additional protection against unwanted (false) write.
program the device. 5 volts is all that is required.
1024 Sectors (128 bytes/sector)
Internal Address and Data Latches for 128 Bytes
Time to Rewrite Complete Memory: 10 s
Typical Byte Program Cycle Time: 80 µs
100 µA CMOS Standby Current
Data Retention: 10 years
The Chip Enable input must be low to enable all read/program operations
on the device. By setting CE high, the device is disabled and the power
consumption is extremely low with the standby current below 100 µA.
The Addresses are used to select an 8 bits memory location during a
program or read operation.
The Output Enable input activates the output buffers during the read op-
The Write Enable input initiates the programming of data into the memory.
Data Input/Output pins are used to read data out of the memory or to
program Data into the memory.
by both CE and OE on low and terminated by either CE or OE returning
high. The outputs are at the high impedance state whenever CE or OE
returns high. The two line control architecture gives designers flexibility in
preventing bus contention.
address is latched internally on the falling edge of the CE or WE, which-
ever occurs last. The data is latched by the rising edge of CE or WE,
whichever occurs first. Once a programming cycle has been started, the
internal timer automatically generates the program sequence to the comple-
tion of the program operation.
a sector is to be changed, data for the entire sector must be loaded into the
device. Any byte that is not loaded during the programming of its sector will
be erased to read FFh. The programming operation of the 29C010 allows
128 bytes of data to be serially loaded into the device and then simulta-
neously written into memory during the internally generated program cycle.
After the first byte has been loaded, successive bytes of data must be
loaded until the full sector of 128 bytes is loaded. Each new byte to be
written must be loaded within 300 µs of the previously loaded byte. The
sector address defined by the addresses A7 - A16 is latched by the first
CE or WE falling edge which initiates a program cycle and they stay latched
until the completion of the program cycle. Any changes in the sector ad-
dresses during the load-program cycle will not affect the initially latched
sector address. Addresses A0 - A6 are used to define which bytes will be
loaded within the 128 bytes sector. The bytes may be loaded in any order
that is convenient to the user. The content of a loaded byte may be altered
at any time during the loading cycle if the maximum allowed byte-load time
(300 µs) is not exceeded. All the 128 bytes of the page are serially loaded
and are programmed in a single 10 ms program cycle
cycle to the host system. During a program cycle, an attempted read of the
last byte loaded into the page will result in the complement of the loaded
byte on I/O7, i.e., loaded 0 would be read 1. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may
be started. DATA Polling may begin at any time during the programming
mining the end of a programming or erase cycle. During a program
or erase operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining
the toggle bit may begin at any time during a program cycle.
HIGH by the use of the CHIP CLEAR operation. By setting CE to low, OE
to 12 Volts, and WE to low, the entire memory array can be cleared (written
HIGH) within 20 ms. The CHIP CLEAR operation is a latch operation mode.
After CE, WE, and OE get the CHIP CLEAR process started, the internal
chip timer takes over the CHIP CLEAR operation and CE, OE, or WE
becomes free to be used by the system for other purposes.
the memory against inadvertent programming:
the chip is inhibited for whatever input conditions.
b) Noise protection - A WE, OE, or CE pulse of less than 10 ns in width is
not able to initiate a program cycle.
c) Write inhibit - Holding OE at low, or CE at high, or WE at high inhibits the
The device is delivered to the user with the software data protection DIS-
ABLED, i.e., the device will go to the program operation as long as Vcc
exceeds 3 V and CE, WE, and OE inputs are set at program mode levels.
The 29C010 can be automatically protected against an accidental write
operation during power-up or power-down without any external circuitry by
enabling the software data protection feature. This feature is enable after
the first program cycle which includes the software algorithm. After this
operation is done the program function of the device may be performed
only if every program cycle is preceded by the software algorithm. The
device will maintain its software protect feature for the rest of its life, unless
the software algorithm for disabling the protection is implemented.
ables the memory to provide the user with additional features:
internal EEPROM fuses during the first page write cycle. These EEPROM
fuses will reject any write attempts of new pages of data, unless the three
dummy data writes are repeated at the beginning of any page writes.
normal program operation. A violation of the three steps program protect
sequence in data or address timing and content will abort the procedure
and reset the device to the starting point condition.
of a standard program cycle. If no additional page data is added to the
three dummy data writes, the software data protect enable procedure will
be aborted. The data protect state will be activated at the end of the pro-
gram cycle. 128 bytes of data must be loaded during a Software Data
Protection Enable cycle.
data programming sequence to disable the software data protect feature
described in a). The six step sequence shown in Table 2 must be per-
formed at the beginning of a program cycle. A violation of the six step
program sequence in data or address timing and content will abort the
procedure and reset the chip to the starting point condition. After a soft-
ware data protect disable cycle including the six step sequence has been
performed, the 29C010 does not require the use of three dummy loads
described in a) for the following program cycle. The device is at the soft-
ware data protect disabled state.
is performed, if no additional bytes of data is added after the six-step write
sequence, the software data protect disable procedure will be aborted.
The data protect state will be deactivated at the end of the program period.
128 bytes of data must be loaded during a Software Data Protection dis-
data writing to perform a chip clear operation. Table 3 shows the six step
write sequence to perform the software chip clear operation:
device automatically activates its internal timer to control the chip erase
cycle; typically takes 20 msec. After a software chip clear operation has
been completed, all 1024K bit locations of memory show high level at
read operation mode.
gram cycle. Table 4 shows the six steps needed to perform the autoclear
programming time to typically 40 µs per byte. The program cycle using
software autoclear disable mode is usually used after a chip clear or a
software chip clear operation. At the end of the six step sequence, the
autoclear before program is disabled and will stay that way unless a power-
down occurs or the software autoclear enable procedure is initiated.
either by Vcc power-down or by software autoclear enable mode. Table 5
shows the six step page procedure needed to enable software autoclear
Input Rise and Fall Times : < 10 ns
Input Pulse Level : 0.45 V to 2.4V
these or any other conditions above those indicated in the operation sec-
tion of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
with respect to Vss